In the evolved oscillator experiment of the previous section, each node had a
slightly different input 
output time delay, crudely modelling
the propagation delays of the reconfigurable blocks of an FPGA. The delays
were initially randomly chosen but then held fixed during the experiment. If
the delays of the final evolved circuit were re-randomised then the
behaviour was totally destroyed, and the circuit was no better than a randomly
generated one: it relied on the particular time delays present during its
evolution. Extrapolating to real intrinsic hardware evolution, it can be
expected that all of the detailed physics of the hardware will be brought to
bear on the problem at hand: time delays, parasitic capacitances, cross-talk,
meta-stability constants and other low-level characteristics might all be used
in generating the evolved behaviour.
The exploitation of all of the hardware's physical properties must be traded against sensitivity to variations in them. Some tolerance is essential because of the inevitable changes over time due to fluctuations in the temperature or power supply, for example, or to the various on-chip ageing phenomena. In addition, if an evolved design is to be implemented on more than one device (as in a commercial application), then it must not be affected by properties that vary from chip to chip. The required tolerance can be evolved by making sure that the properties in question actually do vary while the fitnesses are being evaluated. This might involve purposely varying the temperature or power supply during evaluations and/or carrying out multiple evaluations on different (nominally identical) reconfigurable devices. An alternative to evaluating over several separate devices is to use the same reconfigurable hardware to instantiate the circuit in different ways: translating or rotating it on an FPGA for example. Extending that idea, a genetic encoding could be used which forces the use of repeated structures, so that each structure must cope with the characteristics of all of the places in which it occurs. Another alternative would be to use further adaptation each time the evolved circuit is transferred from one reconfigurable device to another.
The introduction of a fault can be seen as an extreme form of variation in the device's properties: Section 19 will describe a real application of the `further adaptation' approach to coping with a fault. It may also be possible to use the evolutionary fault tolerance mechanisms described in Section 14 to give tolerance to normal device variations.
Even when forced to produce a circuit with tolerance to some range of variations, there is still room for intrinsic EHW to exploit detailed hardware characteristics much more than conventional design does. Traditional design methods cannot proceed far with precise descriptions of the physics of the individual components (eg. transistors) before abstraction and modularisation need to be invoked to make the problem tractable, as discussed above. The `try it and see' opportunistic nature of intrinsic EHW is not subject to this difficulty, so the detailed behaviours of the components can be integrated usefully to give rise to the required overall performance. This paper largely concentrates on the use of digital reconfigurable devices because these are currently available off-the-shelf, but we can now see that the advantages of intrinsic EHW over conventional design are even greater for analogue systems. Analogue FPGAs are being developed [25] and will be a fruitful avenue for EHW research in the future.