Further Design Issues

All of the FPGAs except that on the PCI card are situated in separate housings to the PC, to allow for the large heatsinks, good airflow, etc., involved in thermal regulation. For maximum evolution speed, fitness evaluations need to take place on all FPGAs simultaneously. It has been observed in earlier experiments that some circuits arising in the intermediate stages of evolution oscillate wildly, potentially inducing interference on any wires connected to the FPGA. Evolved circuits have also sometimes shown susceptibility to picking up on the activity of FPGA pins to which they should have no direct access, such as configuration control signals. Therefore, all signals common to more than one FPGA are optically isolated to prevent evolved circuits (even multiple instantiations of the same configuration) from interacting during parallel fitness evaluations. The spatial separation of the PC and the FPGAs, along with the need for optical isolation of all common signals, makes the use of the XC6216's serial interface attractive, despite being slower than the parallel mechanism normally used.

The custom-made interface card in the PC accepts a 2Kbyte buffer of address+data pairs, and transmits them serially with appropriate timings. Using only 4 wires per FPGA, the interface allows configurations to be broadcast to any combination of FPGAs, including all or just one. The programmable clock generator of the PCI card is run at 6MHz to drive the serial configuration. The clock is only run for the minimum number of periods necessary for configuration, so that during fitness evaluations it is inactive and cannot interfere with the evolved circuits in any way. The configuration arrangement is arbitrarily expandable to more FPGAs, or to other members of the family (eg. XC6264), and is easily fast enough for the type of experiments planned.

Some of the FPGAs are mounted in zero insertion-force sockets to allow other devices to be easily substituted, to test for generalisation for example. Because of the potentially unruly behaviour of the circuits, careful attention is given to power-supply decoupling throughout. The host PC runs the GA and the PD thermocontrollers, manages configuration and fitness measurement, can control the temperature setpoints and programmable PSU voltages, and can measure current consumption on the programmable PSU and on the PCI card. This gives maximum flexibility in experimental design, as well as for the centralised logging of data for later analysis.