Results and Discussion

Taking the final population (generation 5000) of 50 individuals evolved for the tone-discrimination task on just one FPGA (see §1), evolution was continued with overall fitness now being the mean of the individual fitnesses measured on the five different FPGAs. The other experimental details remained the same. FPGA 1 was the identical device used in the earlier experiment -- but now at $60^{\circ}$C instead of ambient temperature -- and the $10\times 10$ circuit's position on that FPGA was unchanged. Fig. 5 shows the initial response to the new selection pressure for robustness.

 

Figure 5: Performance on the five FPGAs (Fig. 3) of the best overall individual in the population, at each generation. Intensity is proportional to performance, with dark black being near-perfect and white the worst possible.

Initially, there were some individuals in the population that performed better on FPGAs 2 and 5 than any did on the original chip at its newly elevated temperature. This is surprising as 2&5 are both from a different foundry, and 2 was at $12^{\circ}$C. Quickly, however, good performance was regained on the original chip at its new temperature. Within 300 generations, individuals emerged that had respectable performance on FPGAs 1,2 and 4. This is extremely promising, as these conditions include: {Yamaha silicon, $60^{\circ}$C}, {Seiko silicon, $12^{\circ}$C }, and {Seiko silicon, $15^{\circ}$C/cm gradient}. Most of the time, for any given FPGA there would be at least one individual in the population achieving fair performance on it; the difficult part is finding single individuals scoring well in all conditions. The role of population diversity appears worthy of further investigation.

At the time of writing, the experiment has not progressed beyond what is shown here, so it is too early to begin to answer the questions of §3, but the signs are encouraging. In particular, circuits coping with some extremities of the operational envelope have been found without having to increase the $10\times 10$ area of FPGA made available to them -- they are still extraordinarily compact. There is, however, a long way to go. This partially successful adaptation to operation in some extreme conditions was relatively rapid compared to the initial evolution of the behaviour on just one chip; it might be suspected that complete success will take much longer. The apparent ease of adapting a circuit (or population) to a single new set of conditions, although not the goal of this project, could conceivably be useful in some applications.

This paper has introduced the notion of unconstrained intrinsic evolution for robustness within an operational envelope. An experimental arrangement has been described in detail which permits a controlled and scientific exploration of this research avenue, to illustrate its feasibility and promise. Early results are positive: even if complete success should not be achieved, it is already clear that experiments within this framework will be illuminating.
This work is supported by EPSRC, with equipment donated by Xilinx and Hewlett Packard. Related work is supported by British Telecom and Motorola. Thanks to all.