Case Study:
Evolving a Single-Electron NOR Gate

We begin by investigating the evolution of a single-electron NOR gate because a simulator suitable for this purpose is available [25], a NOR gate is a simple circuit but a universal logic primitive, and single-electron NOR gates have been studied before [5]. Evolution of a small building-block to be used repeatedly in larger systems is attractive: The task is susceptible to contemporary evolutionary algorithms, which can be allowed to exploit subtly the physics of the medium at a fine level of detail, while leaving the higher-level logical composition of the building-blocks to more conventional methods.

In a single-electron circuit, the movement and position of a single or small number of electrons are controlled; in particular the controllable quantum-mechanical tunnelling of electrons across thin insulators formed at the nano- or meso- scale is exploited. Circuit design and construction based around these `tunnel junctions' (and other such devices) has been much explored since the late 1980's, but still faces major challenges. A popular account is provided in [11], and a database of publications is available at [1].

The designs were represented as a two-dimensional array of nodes. The size was kept fixed at 7 rows $\times$ 4 columns. Between each pair of nodes was a component selected from the set $\left\{ \mbox{\sc none, capacitor, junction, wire} \right\}$, where JUNCTION refers to a tunnel junction. Associated with each capacitor or junction was a real-valued capacitance in the range $\left[ 4.0\times10^{-19}, 1.0\times10^{-13} \right]$F. Also associated with each junction was a tunnel resistance in the range $\left[ 5.0\times10^{4}, 1.0\times10^{9} \right]\Omega$. NONE indicated the absence of a component between two nodes. A WIRE between two nodes was a virtual construct, signifying that the connected nodes should be amalgamated into one when the circuit is to be evaluated. Taking an example from the experiment to follow, Fig. 3 shows the representation of a circuit as manipulated by the evolutionary algorithm, while Fig. 4 shows the actual design so represented.

The top row of nodes was supplied with a constant bias voltage $V_b$ in the range $\left[ -1.0\times10^{-4}, -1.0\times10^{-6} \right]$V. The bottom row of nodes was connected to 0V. No components were allowed between the nodes in the top row, or between the nodes in the bottom row.

The two inputs to the NOR gate were always attached to the same nodes, as seen at the left in Fig. 3. Also shown is the fixed position of the `preferred' output node. The actual output was taken from a valid output node closest in Manhattan distance to the preferred output node. A node was a valid output node if there was a connected path to it from each of the inputs that was at no point shorted to $V_b$ or 0V. In the case of multiple valid output nodes of equal minimum distance from the preferred position, the one furthest to the right (and furthest down if there was still a tie) was chosen.

Although the array of nodes was fixed in size, the use of NONE and WIRE components, together with the output position selection method, gave considerable freedom for circuits to be of different sizes within the boundaries.

Underlying the choice of circuit representation was the notion that elements that interact should be adjacent to each other, since the usual action of a `wire' is difficult to achieve [9]. To this end, regular cellular architectures have been proposed, e.g. [2]. Within a primitive (which may be repeated in some sort of array), the representation scheme adopted here is more flexible than a regular array, yet interacting elements can still be brought next to each other through a topology-preserving deformation of the layout once nodes connected by a virtual WIRE have been amalgamated.

The fitness of a candidate circuit was evaluated by applying the voltage waveforms shown in Fig. 1 to the inputs, while monitoring the voltage at the output node. The input voltage sources were coupled to the circuit through fixed series capacitors of $3.333\times10^{-13}$F in a small attempt to model the situation where the inputs would be driven by the outputs of similar adjacent NOR gates; the output node was loaded by a 1pF capacitor to ground. These arrangements can be seen in Figs. 3 and 4.

Figure 1: The input waveforms for a fitness evaluation (dotted and dashed) and the ideal output $V_{ideal}(t)$ (solid).

Also shown in Fig. 1 is the ideal (target) output voltage waveform $V_{ideal}(t)$. If the actual observed output of a candidate circuit was $V_{out}(t)$, then its fitness over the trial of length $T$ was calculated as:

$$\textrm{Fitness} = \frac{-1}{T \left\vert V_{true} - V_{fals... ...nt_{0}^{T} \left\vert V_{out}(t) - V_{ideal}(t) \right\vert dt$$ (1)

or $-1.0\times10^{6}$ if the individual was not viable. An individual was unviable if no valid output node could be found, or if an input was shorted to 0V or $V_b$. The fitness of a viable circuit, given by the equation, is just $-1\times$ the normalised mean error of the output voltage over the trial, so the perfect circuit would score 0.0.

The voltages $V_{true}$ and $V_{false}$ defining the logic levels of both the inputs and the ideal output could be varied by evolution (along with $V_b$) as part of the description of an individual circuit. They could assume any values, subject to the constraint that $\left\vert V_{true} - V_{false} \right\vert \geq 0.75V_b$, and they were initially randomly chosen from the interval $\left[ V_b, 0.0 \right]$V (again subject to the constraint). The input waveforms have nonzero rise and fall times, whereas the ideal output responds instantly at a logic threshold of $\left( V_{true} + V_{false} \right) / 2$. This provides a selection pressure for the evolution of noise margins.

The circuits were simulated using the SIMON package [1,24,25], with the parameter settings given in the footnote.¹The first phases of the experiment were conducted at absolute zero temperature (0K), and neglected co-tunnelling (only first order tunnelling was simulated). In the Phase 2 we will go on to describe how the temperature can be increased and higher-order tunnelling accounted for.