Abandoning the external clock can reap even more rewards than were mentioned above. A clocked digital system is a finite-state machine, whereas an unclocked (asynchronous) digital system is not. To describe the state of an unclocked circuit, the temporal relationships between its parts must be included. These are continuously variable analogue quantities, so the machine is not finite-state. This theoretical point gives a clue to a practical advantage: in an unclocked digital system, it is possible to perform analogue operations using the time dimension, even when the logic gates assume only binary values (see for example, the pulse stream technique [21, 22]).
In the previous section, I argued that when producing circuits by evolution rather than design, the use of a clock is often an unnecessary limitation on the way in which the natural dynamics of the components can be used to mediate robot behaviour. This is not always the case -- electronic components usually operate on time-scales much smaller than would be useful to a robot; unless the system can evolve such that the overall behaviour of the components (when integrated into the sensorimotor feedback loop of the robot) is much slower than the behaviour of individual components, then a clock (perhaps of evolvable frequency) will be required to give control over the time-scales. (Sometimes, the use of a clock can expand the useful dynamics possible from the evolving circuit.)
A simulation has been performed to investigate whether a genetic algorithm can evolve a recurrent asynchronous network of high speed logic gates to produce behaviour on a time-scale that would be useful to a robot. The number of logic nodes available was fixed at 100, and the genotype determined which of the boolean functions of Table 1(a) was instantiated by each node (the nodes were analogous to the reconfigurable logic blocks of an FPGA), and how the nodes were connected (an input could be connected to the output of any node, without restriction). The linear bit-string genotype consisted of 101 segments (numbered 0..100 from left to right), each of which directly coded for the function of a node, and the sources of its inputs, as shown in Table 1(b). (Node 0 was a special ``ground'' node, the output of which was always clamped at logic zero.) This encoding is based on that used in [2]. The source of each input was specified by counting forwards/backwards along the genotype (according to the `Direction' bit) a certain number of segments (given by the `Length' field), either starting from one end of the string, or starting from the current segment (dictated by the `Addressing Mode' bit). When counting along the genotype, if one end was reached, then counting continued from the other.
| BITS | MEANING |
| 0-4 | Junk |
| 5-7 | Node Function |
| POINTER TO FIRST INPUT | |
| 8 | Direction |
| 9 | Addressing Mode |
| 10-15 | Length |
| POINTER TO SECOND INPUT | |
| 16 | Direction |
| 17 | Addressing Mode |
| 18-23 | Length |
At the start of the experiment, each node was assigned a real-valued
propagation delay, selected uniformly randomly from the range 1.0 to 5.0
nanoseconds, and held to double precision accuracy. These delays were to be
the input-output delays of the nodes during the entire experiment, no matter
which functions the nodes performed. There were no delays on the
interconnections. To commence a simulation of a network's behaviour, all of
the outputs were set to logic zero. From that moment onwards, a standard
asynchronous event-based logic simulation was performed [19], with
real-valued time being held to double precision accuracy. An equivalent
time-slicing simulation would have had a time-slice of 
seconds, so
the underlying synchrony of the simulating computer was only manifest at a
time-scale 15 orders of magnitude smaller than the node delays, allowing the
asynchronous dynamics of the network to be seen in the simulation. A
low-pass filter mechanism meant that pulses shorter than 0.5ns never happened
anywhere in the network.
The objective was for node number 100 to produce a square wave oscillation of
1kHz, which means alternately spending 
seconds at logic `1'
and at logic `0'. If k logic transitions were observed on the output of node
100 during the simulation, with the 
transition occurring at time
seconds, then the average error in the time spent at each level was
calculated as :
For the purpose of this equation, transitions were also assumed to occur at
the very beginning and end of the trial, which lasted for 10ms (but took very
much more wall-clock time to simulate). The fitness was simply the reciprocal
of the average error. Networks that oscillated far too quickly or far too
slowly (or not at all) had their evaluations aborted after less time than
this, as soon as a good estimate of their fitness had been formed. The genetic
algorithm used was a conventional generational one [5], but used
elitism and linear rank-based selection. At each breeding cycle, the 5 least
fit of the 30 individuals were killed off, and the 25 remaining individuals
were ranked according to fitness, the fittest receiving a fecundity rating of
20.0, and the least fit a fecundity of 1.0. The linear function of rank
defined by these end points determined the fecundity of those in-between. The
fittest individual was copied once without mutation into the next generation,
which was then filled by selecting individuals with probability proportional
to their fecundity, with single-point crossover probability 0.7 and mutation
rate 
per bit.
The experiment succeeded. Figure 2 shows that the output after
40 generations was approximately 
thousand times slower than the
best of the random initial population, and was six orders of magnitude slower
than the propagation delays of the nodes. In fact, fitness was still rising at
generation 40 when the experiment was stopped. The final circuit
(Figure 3) was exploiting the characteristics of its
``implementation'' -- if the propagation delays were changed, it reverted to
behaviour similar to that at the first generation. A spike-train, rather than
the desired square-wave was produced, allowing the phenomenon of spike
trains of slightly different frequencies beating together to produce a much
lower frequency (but it is difficult to gain the massive reduction in
frequency required and yet produce a regular output). The entire network
contributes to the behaviour, and meaningful sub-networks could not be
identified.
Figure 2: Output of the evolving oscillator. (Top) Best of the initial random
population of 30 individuals, (Bottom) best of generation 40. Note
the different time axes. A visible line is drawn for every output spike, and
in the lower picture each line represents a single spike.
Figure 3: The evolved 4kHz oscillator (unconnected gates removed, leaving
the 68 shown).
This simulation, although quite an unrealistic model of the evolution of a real FPGA configuration, has shown how evolution can assemble high speed components to produce behaviour on a time-scale that approaches that useful to a robot. It exploits the characteristics of the implementation, and does not require the imposition of spatial or temporal constraints such as modularisation or clocking. The style of solution adopted (the beating of spike trains) is an analogue operation over the time axis, and would have been more difficult in a discrete time system.
