The `Evolvatron'

The `Evolvatron' is a tool that can provide an evolutionary selection pressure for robustness, without having to prejudge how this should be achieved. For example, [66] observes that analogs of many of the strategies for thermal robustness found in animals, from a behavioural level down to the molecular, could also arise in unconstrained evolved electronics subject to this selection pressure. Some of these strategies are very different to those practiced in conventional electronics design.

Section II described how orthodox methods bring about robustness by adopting general design constraints. In contrast, the evolutionary goal is to produce mechanisms for robustness that are tailored to the task, the structure and dynamics of the circuit, and -- in turn -- the natural physical resources of VLSI. This approach is less restrictive to design-space exploration, and can potentially find holistic strategies for robustness that are superior in their particular domain. By `holistic' we mean a strategy not only tailored to the situation, but which also emerges at the system-level, not necessarily demanding robustness of all of the parts. Here, robustness is part of the target of the evolutionary design process, whereas for conventional methods it is mostly a constraint placed upon the design process itself.

Figure 25: The `Evolvatron'.

Figure 26: An example of an achievable set of test points within an operational envelope.

The Evolvatron is shown in Fig. 25, and is fully described in [68]. It consists of an expandable collection of XC6216 FPGAs, which are maintained in different conditions. Fig. 26 summarises the conditions currently provided in the pictured machine. Using five chips, from two different foundries, a selection is provided of thermal conditions, power-supply voltages, output loads, host$\Rightarrow$FPGA interfaces, chip packages, and positionings of the $10\times 10$ evolved region within the array.

For a fitness evaluation, a circuit is downloaded to each of the chips, which are then tested simultaneously at the target task. The evaluation function combines the five scores so as to give a measure of the circuit's ability to perform the task in all of these conditions: the selection pressure for robustness. Preliminary results for the tone discrimination task are encouraging [68]. The primary research questions are:

• What resources are needed for robustness? Are stable off-chip components required? Is it necessary to provide a stable oscillation as an extra input to the evolving circuits? Such a clock would be a resource, to be used in any way (or ignored) as appropriate, rather than an enforced constraint on the system's dynamics as in synchronous design.
• Can generalisation over an entire, practical, operational envelope be achieved through evolution in a relatively small number of different conditions?
• Given the experimental arrangement described herein, is the evolution of a robust circuit more difficult than of a fragile circuit evolved on just one FPGA? (An apparently harder task is not necessarily more difficult for evolution, depending on the pathways available for evolutionary change.) Does it make sense gradually to increase the diversity and span of the operational envelope during evolution, or should the population be exposed to a representation of the complete operational envelope right from the beginning?
• If robust circuits are evolved, how do they work? Do they look more like conventional circuits? Are they still smaller?