- ... Zebulum
- Centre
for Computational Neuroscience and Robotics, and
Centre for The Study of Evolution,
School of Cognitive & Computing Sciences,
University of Sussex, Brighton BN1 9QH, UK.
(email: adrianth, paulla, ricardoz @sussex.ac.uk)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
- ... reality.
-
Although charge is quantised, and these charges often move through periodic
atomic lattices having discrete energy levels, at the scale addressed by
contemporary circuit design we may consider currents and voltages as
continuous [22]. This could change in the future if meso/nano-scale
electronics becomes practical; it might then be possible to exploit physical
quantisation to implement digital computations [23].
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
- ... (H3).
- It is not essential to adopt such a
radical unconventional stance to begin to tackle this issue. For instance,
Miller & Thomson [36] incorporate geometric layout considerations
into evolutionary design of digital logic.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
- ... present.
- If the GA was left to
run, then these completely-tolerant solutions would be lost again as the GA
concentrated entirely on improving performance in the presence of the current
most serious fault -- even if that performance was already satisfactory. No
claims are made regarding the generality and reliability of this particular
algorithm used here for illustrative purposes.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
- ...
electronics
-
TECHNICAL NOTES: The circuitry was mounted wire-wrapped on
an ISA (Industry Standard Architecture) card (Fig. 14).
The analogue integrator was of the basic op-amp/resistor/capacitor type, with
a MOSFET to reset it to zero [27]. A MC68HC11A0 micro-controller
operated this reset signal (and that of the FPGA), generated the tones, and
performed 8-bit A/D conversion on the integrator output. A final accuracy of
16 bits in the integrator reading was obtained by summing (in software) the
result of integration over 256 sub-intervals. Locations in the configuration
memory of the FPGA and in the dual-port RAM used by the micro-controller
could be read and written by the PC via registers mapped into the ISA-Bus
I/O space. The XC6216 device was a pre-production engineering sample.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
- ... inputs.
- The 20MHz oscilloscope
used for the earlier photographs of Fig. 15 was inadequate
for analysis purposes. For the remainder, a Hewlett Packard 54542C
four-channel digital storage oscilloscope was used, which samples at 2
Giga-samples/sec, and is bandwidth limited to 500MHz.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.