The strategy was to evaluate each evolved design not just on one FPGA chip, but on a number of similar devices in a variety of conditions. Initially it was not known how many separate conditions would be needed in order to evolve a circuit that was robust across the whole range of variations. Early results using a prototype of four FPGAs interfaced to the host PC were promising, but prototyping circuit construction technology was found to be inadequate for the reliable operation of such a complex electronic system. This was accentuated since Peltier-effect heat pumps were used to place the temperatures of the FPGAs under software control, introducing thermomechanical stresses and water vapour condensation problems. Some of the chips were heated, and the evolutionary experiments take a period of days, so the system must be fire-safe and reliable to operate unsupervised.
The prototype was replaced by the system shown in Fig. 1.
We designed a printed circuit board (PCB) on which each FPGA could be mounted,
along with some interfacing and circuits to monitor the chip's
behaviour for evolutionary fitness evaluation purposes. The system was
designed to be very sturdy, also minimising electrical noise and
possible interactions between the FPGAs (using optical isolation). A special
interface board was designed for the host PC that can reconfigure the FPGAs
simultaneously (broadcast) or individually with different configurations. The
connection to each FPGA board is a 6MHz serial link, allowing them to be a
distance from the PC for thermal control purposes. One FPGA board is simply
sealed in a bag in a domestic freezer, while others still have temperature
regulation under software control. The development of this hardware and the
supporting software was a major task.
We ran evolutionary experiments using five FPGAs, representing a variety of: fabrication processes and variations, temperatures, power-supply voltages, physical device packages, output load conditions, placements of the evolved circuit within the FPGA's array, and electrical interface environment (one FPGA was on a commercial PCI board plugged inside the PC). The task was a simple audio-tone discrimination, adopted in the earlier experiments as a simple task raising all of the research issues, and being a potential stepping-stone to more advanced signal processing and pattern recognition.
The experiment was successful, resulting in a highly robust evolved circuit. To determine the extent of this robustness, and whether or not evolution had simply rediscovered conventional design rules, the design was simulated in a standard commercial digital simulator, using a rough model of the logic gates in the FPGA's cells. Surprisingly, this reveals the circuit to be a well-behaved asynchronous digital design, yet no digital design rules had been imposed: evolution was crafting a continuous-time recurrent network of logic gates, with a 6MHz clock signal being available just as an extra resource to be used in any way or ignored.
This is the primary result of the project. Using our methods, robust circuits can be evolved that are still of a radically new kind, giving the potential to be superior in some applications. In our case the circuit evolved to be a well-behaved asynchronous digital design, yet it was not structured according to any standard design principles. In fact, without our evolution under multiple sets of environmental conditions, it is not clear that any predefined design rules could have been imposed that would guarantee that all evolved circuits would be robust, yet which would have allowed this circuit design. We see that evolution can explore new territory even in digital design, whereas it may previously have been thought that this potential lay only in the less structured field of analog design.
In parallel, Thompson was working with Layzell (below) on novel analysis techniques for evolved circuits. Circuits not designed according to known principles, and which may also be difficult to observe experimentally if implemented on a reconfigurable chip, are not amenable to any one electronics analysis method. We developed the idea of bringing together a whole suite of formal and empirical analysis techniques, including new ones such as the inspection of circuit behaviours throughout evolutionary lineages. The body of evidence so formed, while not constituting a full understanding, can be used to answer crucial questions. We took the early circuit evolved on just one chip (this is the most bizarre and mysterious evolved circuit reported to date), and were able to prove that it was free from long term intermittent dynamics, so would be stable in extended use. We developed an understanding of many facets of its operation, and its robustness (or lack of it). We see such analysis as vital in validating and characterising evolved circuits for practical applications.
Layzell used this analysis methodology to extend our earlier work on fault-tolerance in evolutionary electronics scenarios. He showed that if a component is removed from the circuit design that is the best in the final evolutionary population, then even if that `fault' is disastrous for this best individual, in some situations it can be expected that there will be another individual in the population that still performs fairly well with this fault in place. This `population fault tolerance' occurs because of the incremental way in which the circuit is built-up over the course of evolution.
We argued that evolved designs have the potential to be superior in some applications because they are new and different. To realise this, it is sometimes necessary to introduce an explicit quality objective for the evolutionary process, e.g. to minimise size and power-use whilst maximising speed. In a real electronics application there are usually many quality and performance criteria. Zebulum (below) worked with us to show that simple extensions of the existing GA multi-criteria optimisation techniques can also be effective in electronics design.
A final part to this project has been a preliminary study to apply these ideas to enabling future technologies. These difficult but promising technologies, such as molecular computing and nano-electronics, share the need to harness subtle physics to do useful computation. At the microelectronics level of current FPGAs, we have seen evolution achieving this with great facility. Although the automatic design of very large complex systems is beyond contemporary evolutionary methods, EAs could be used to design small computational primitives, or `building-blocks' out of which a larger design could be composed. Thompson is collaborating with C. Wasshuber in the USA, the author of a `single-electron' nanoelectronics circuit simulator, to explore this idea. They have evolved a NOR logic gate that is not yet a practical design, but which has been shown to exploit the thermal energies of the electrons in a way not suggested before in the literature.
All of the details of the experiments, equipment, and methods, have been fully documented in the papers listed on the IGR form.
