Appendix A.
Circuit Diagram of the DSM Evolvable Hardware Robot Controller

This is an extract from "Hardware Evolution" © Springer-Verlag 1998, all rights reserved.

This appendix gives the circuit diagram mentioned in Section 3.3.3. Other hardware details of the `Mr Chips' robot are available from the author: they are a matter of conventional digital design, so are not of direct importance to this book.

With reference to the DSM circuit diagram, Figure 1, the circuit functions as follows. The RAM chip is in fact a MS6130 1k$\times$8 dual-port RAM. One port is used to provide read/write access for the PC, and the other supports the feedback connections of the DSM. The `Genetic Latches' are implemented by 74HCT4053 analogue switches, which - depending on their control bits - select signals either directly, or after they have passed through one of the 74HCT273 latches driven by the genetically specified clock. A separate pair of 74HCT273 registers, which can be written to by the PC, are used to hold these switch settings. The clock of genetically specified frequency is generated by a MC68HC811E2 micro-controller (not shown), referenced to its crystal oscillator by way of a real-time interrupt service routine.

  

Figure 1: Circuit diagram for the DSM evolvable hardware robot controller.

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